One integrated circuit (IC) has output buffers to transmit data signals, for example, onto input/output (I/O) lines of a bus for reception by another IC coupled to the bus. The speed or frequency at which such signals may be reliably transmitted and received depends at least in part on the slew rate, that is the rate of voltage change, with which the signals are driven. An IC driving signals at too fast of a slew rate for a given bus frequency may introduce noise into the I/O lines and therefore limit the ability of a receiving IC to interpret the signals properly. An IC driving signals at too slow of a slew rate for a given bus frequency may also limit the ability of a receiving IC to interpret signals properly as changing signals may not sufficiently transition from one voltage level to another within the time period in which the receiving IC is to interpret signals.
Because the slew rate with which an output buffer drives signals can vary due to, for example, variations in process, supply voltage, and/or temperature (PVT variations) for the output buffer, IC's may be designed to drive signals at reduced frequencies to allow slew rates to vary and/or designed to control slew rates to help maintain them at substantially uniform levels in the presence of PVT variations. One IC controls output buffer slew rates by controlling resistances affecting slew rates relative to the known resistance of a resistor external to the IC.